In a memory device, cell area is the most significant factor which determines the chip size. Reducing memory cell size has a major impact on cost effectiveness and compatibility to packages of previous generations. One important consideration in reducing the size of a memory cell is the configuration of the bit and complementary bit lines. The arrangement of the bit and complementary bit lines impacts the noise and inter-bit line coupling.
There are two conventional arrangements of bit and complementary bit lines. The twisted folded bit line configuration, as shown for example in FIG. 1, has been used in most dynamic random access memory (DRAM) cells because of its noise immunity. In particular, a sense amplifier 104 is coupled to a bit line 106 and a complementary bit line 108 in memory cell array 102. As is shown, the bit lines are twisted, providing reduced inter-bit line coupling. With the recent improvements in semiconductor manufacturing, this configuration has achieved a minimum cell size of 8F2, where F is a minimum feature size.
If the smaller cell size is required to reduce total chip size, an open bit line configuration is often employed. The open bit line configuration has a 6F2 (or 4F2) cell area and provides simple structure. However, the open bit line configuration suffers from noise due to the different location of the bit lines. That is, because the bit line and the complementary bit lines are associated with different arrays, the bit line and the complementary bit lines are exposed to different noise which cannot be cancelled out. Accordingly, the large inherent levels of noise must be reduced to make the open bit line configuration a more acceptable option.
Referring specifically to FIG. 2, a conventional open bit line configuration is shown. A sense amplifier array 202 including bit line sense amplifier 204, shown in more detail in FIG. 3, is located between two cell array blocks. The conventional sense amplifier 301 comprises an amplifier precharge circuit 302 including a pair of transistors 304 and 306 coupled between the bit lines 206 and 208. A voltage bit line equivalent (VBLEQ) voltage level 308 is coupled to the transistors 304 and 306, while a PC signal 310 is coupled to the gates of the transistors 304 and 306, as well as the gate of a transistor 312. The operation of the sense amplifier of FIG. 3 is well known in the prior art.
Referring back to FIG. 2, one of two bit lines 206 or 208 acts as a reference line during sensing operation. Accordingly, dummy edge cell arrays 210 are necessary to match bit line load for the edge bit line sense amplifier array 202 when reading data from an array of cells 212. This dummy edge cell array generally increases the size of the chip. Another critical problem of open bit line configuration is the large level of noise associated with bit lines located in separate arrays. This decreases the sensing margin, making the sensing operation unstable and cell refresh time poor. In addition to array noise, the inter-bit line coupling noise is large in the conventional open bit line configuration, also reducing the sensing margin. This inter-bit coupling cannot be eliminated.
Accordingly, there is a need for an improved bit line configuration to read data from open bit line cells.